Summary

Not many people have a thorough understanding of the internal structure and patterns of GPIO (General Purpose Input and Output) processors. Recently, Baidu has searched for a large amount of information on this part, and there is no consensus on many of these issues.This article lists all the questions that IO involves as far as possible, explains clearly the questions that have definite answers, and puts forward the questions where there are still questions for discussion.

Generally speaking, IO’s functional modes can be roughly divided into three categories: input, output and input-output bidirectional. As the basic input IO, it is relatively simple, the main knowledge involved is the high resistance state; as the output IO, compared with the input complex, the main mode of operation is leak (Open D)Rain mode and Push-Pull mode, this part involves a lot of knowledge points; for input and output IO, the easy confusion is the difference between quasi-bidirectional and bidirectional ports.

Next, we will introduce the details of each mode in this order.

Input IO

The input IO is referred to as input and does not have output function. At this point, the requirement for the input pin is high resistance (high resistance is the same concept as the three state). The types of basic input circuits can be roughly divided into three categories: basic input IO circuits, Schmidt triggered input circuits, and weak pull-up.Input circuit.

Starting with the basic basic input IO circuit, its circuit is shown in Figure 1.

The buffer U1 is a three state buffer with high input impedance and high impedance characteristics. Generally speaking, this buffer is high resistance to the outside, equivalent to the control input does not enable the case, the physical pin and the internal bus is completely isolated, completely does not affect the internal circuit. And controlThe function of the input terminal is to send out the instruction to read the Pin state. The process is shown in Figure 2.

One disadvantage of this basic circuit is that it jitters when reading the jump edge of an external signal, as shown in the following figure.

So the Schmidt trigger input circuit is to solve the above jitter problem, after the Schmidt trigger signal as shown in Figure 4.

Another problem with the input circuit is whether the input level is high or low when the input pin is suspended. When the input signal is not driven, i.e. Floating, any noise on the input pin changes the level detected by the input, as shown in Figure 5..

To solve this problem, a weak pull up resistor can be added to the input pin, as shown in Figure 6.

In this way, when the input pin is suspended, it is pulled up to a high level by the RP, and there is a certain state on the internal bus.

But this structure has some problems. The first obvious thing is that when the input pin is suspended, it reads 1, when the input pin is driven by a high level, and it reads 0 only when the input pin is driven by a low level. That is to say, the way to read 1 is to read “non zero”..

Another problem is that the circuit does not present a high resistance to the outside, in a sense, is also outward output, when the external drive circuit may be different when the error detection results. For example, the external drive circuit is shown in Figure 7, which can output high level or low level by K hitting different ends.

If the circuit shown in Figure 7 is connected to an input pin with a weak pull-up resistance, the structure is shown below.

According to Ohm’s law, the level at the test point is，So the input signal measured by CPU is high, while the external driving circuit wants to output the low level. The reason for this error is that the structure of the input circuit is not really high resistance, or that the input IO is actually output, and affect the external input circuit.

The occurrence of this situation also explains: the signal before and after two levels of transmission, why the need for small output impedance, large input impedance. In this case, the output impedance of the peripheral drive circuit is very large, reaching 100 Kohm, and the input impedance is not large enough, only 10 Kohm, so it appears.The problem. If the input impedance of the input is really high (infinite), as shown below, there will be no problem.

The aforementioned input circuit with weak pull-up is the case of quasi-bidirectional ports mentioned in subsequent chapters.

Output IO

IOThe two main modes of the output circuit are Push-Pull Output and Open Drain Output.

Push pull output (Push-Pull Output)

Push-pull output structure is controlled by two triodes or MOS transistors by complementary signals, the two transistors always keep one in the cut-off state, the other in the conduction state. As shown in Figure 10.

The biggest characteristic of push-pull output is that it can really output high and low level, and it has driving ability at both levels.

Additional Description: the so-called driving power refers to the ability to output current. For driving large loads (i.e. the smaller the load resistance, the greater the load), such as IO output 5V, the drive load resistance is 10ohm, so according to Ohm’s law can normally load current of 0.5A (calculation)The output power is 2.5W). Obviously, the average IO can’t have such a large driving power, that is, it can’t output such a large current. The result is that the output voltage will be pulled down to a nominal 5V.

Of course, if only digital signal transmission, the next stage of the input impedance is theoretically best high resistance, that is, only the transmission of voltage, basically no current, there is no power, so there is no need for a large driving capacity.

For push-pull output, the current flow direction of high and low output is shown in Figure 11. Therefore, compared with the open drain output introduced later, the output power of high power is much stronger.

Open Drain Output (open drain output)

Often said with push-pull output is the opposite of open leakage output, the most common difference between open leakage output and push-pull output is that open leakage output can not really output high level, that is, high level does not have driving capacity, need to use external pull-up resistance to complete external drive. From the internal structure and principle, explain why.The open drain output and output have no driving power at high power level, and the difference between push-pull output and further comparison.

First, we need to introduce some open drain output and open set output. The principle and characteristics of these two outputs are basically similar, the difference is that one is the use of MOS transistors, in which the “leakage” refers to the MOS transistor drain; the other is the use of a triode, in which the “collection” refers to the MOS triode collector. This twoIn fact, they are all output modes corresponding to push-pull output. Because of the use of MOS transistors, the word “open-leak output” is often used instead of open-leak output and open-set output.

The introduction starts with the output of the open set, and its principle circuit is shown in Figure 12.

The circuit on the left of Figure 12 is the most basic of the open-set (OC) output. When the input is high, the NPN transistor is turned on, and the Output is pulled to GND and the output is low; when the input is low, the NPN transistor is closed, and the Output is equivalent to the open circuit (output high resistance). highHigh resistance is output at the level (high resistance, three states, and floating mean the same), and there is no external drive capability. This is the biggest feature of open-leak and open-set output, how to use this feature to complete a variety of functions will be introduced later. Although the circuit has completed the output function of the open set,Input will be high, output is low, input is low and output is high.

Fig. 12 the circuit on the right has used a transistor to complete the “reverse phase”. When the input is high level, the first transistor is turned on, and the input of the second transistor is pulled to GND, so the second transistor closes and the output is high resistance; when the input is low level, the first transistor closes, and so on.The input of the second triode is pulled up to a high level by the pull-up resistance, and the second triode is turned on and the output is pulled up to GND. In this way, the input and output of the circuit are in phase.

Next, we introduce the circuit of open drain output, as shown in Figure 13. The principle is basically the same as the output of the open set, but the transistor is replaced by MOS.

When the MOS transistor is closed, the open-drain output circuit outputs a high level, and when the load is connected, the current flow is from an external power source, which flows through the up resistance R._PU，Flow into the load and finally enter GND.

1. An obvious advantage of this characteristic of open-drain output is that it is easy to adjust the output level, because the output level is completely determined by the power level connected by the pull-up resistance. Therefore, where the level conversion is needed, it is very suitable to use open drain output.
2. Another advantage of the open-leak output feature is that it can implement the “wire-to-wire” function. The so-called “wire-to-wire” refers to the direct connection of multiple signal lines. Only when all the signals are high-level, the combined bus is high-level; as long as any one or more signals are low-level, the bus is low.Level. Push-pull output is not feasible, if the high level and low level together, there will be current backfilling, damage the device.

The difference between push-pull and open drain output

Bi-directional IO

Many processors have pins that can be set as bidirectional ports, requiring both output and external input. It’s a bit difficult in principle to do both, starting with the internal structure of the processor’s leaky output IO port, as shown in Figure 16.

Bidirectional open drain IO

However, the structure of Figure 16 has been slightly modified, as shown in Figure 17, which is called a bidirectional leak IO structure. The change is to connect the input drive buffer to the PIN.

When the output of the structure is “1”, T1 is disconnected, and pin exhibits high resistance, so there is no problem as input pin. But if T1 is turned on when the output of this structure is “0”, then pin is short-circuited to the ground, that is, whatever signal is input from the outside, U2 reads back all the low. So for this reasonThe structure, if you need to use as an input pin, you must output “1” to U1 before you can read the external pin data.

Quasi bidirectional open drain IO

Quasi-bidirectional ports are also mentioned in many literatures. In fact, the quasi-bidirectional port is a pull-up resistance added to the structure of Figure 17, as shown in Figure 18.

This structure has the following similarities and differences compared with Figure 17:

1. When used as an input pin, it is also necessary to write “1” to U1 in order to achieve the purpose of disconnecting T1. Therefore, the need to write “1” ahead of time is not the difference between two-way IO and quasi two-way IO. Both of them need to write “1” ahead of time when doing input ports.
2. The bi-directional port is a real high impedance state when it is input, and the quasi-bi-directional IO is not a high impedance when it is input.
3. The quasi bidirectional port reads the input state, and the default is high. That is to say, the method of judging the external input signal is “not low but high.” That is, the structure can only identify the external low level accurately, and can not distinguish between the suspended and the real high. So if you read 0, you think external is 1.

Push-pull output as bidirectional IO

If the push-pull output structure is used in the output part of the bidirectional port, then the input must be both upper and lower pipe ports to become high resistance, as input.

51P0 port of MCU

In the discussion of two-way ports, the more complex one is the P0 port of the 51 microcontroller. Here we will discuss the P0 port structure and working principle of the 51 single chip microcomputer in detail.

P0The internal structure of the port is shown in Figure 19.

The internal structure is complex, including the following devices:

1. U1：And the door. One input is connected to the control line, and the other input connects the address / data signal. Because of the characteristics of the and-gate, when the control line is 1, the output of the gate is consistent with the level of the address/data signal; if the control line is 0, the output is constant. The control signal line is equivalent to the enable signal of the gate.
2. U2：The inverters output signals are inverting signals of address / data signals.
3. U3Both U6 and U6 are three-state buffers with control inputs and high impedance characteristics, which are used to present high impedance states to the outside. When the control terminal is enabled, the level of the external signal can be read into the data bus.
4. U4：The purpose of the latch is to control the time of pin output signal.
5. U5：Analog switch can control whether the input signal of V2 is Q non-output from latch U4 or output from inverter U2.
6. V1And V2 are two MOS tubes respectively.

After understanding the various independent devices, we begin to introduce the working principle of the work in various modes.

P0For address / data line:

When P0 is the address/data line, it is the address and data multiplexing bus. P0 needs to output the address and read back the data signal.

When P0 needs to output address information, the control signal of U1 is 0, and the analog switch U5 is connected to the output of U2 inverter. So the signal from the address signal line is 1, and the input signal from the control line “1” to the V1 is “1” and the V1 cuts off. After the address signal “1” is reversed,The output of the analog switch to the input of V2 is “0” and V2 is on, so the pin output is “0” as shown in Figure 20.

The signal from the address signal line is 1, and the input signal from the control line “1” to the V1 is “0” and the V1 is on. After the address signal “0” is inverted, the analog switch outputs to the input of V2 as “1” and V2 cuts off, so the situation is shown in Figure 21, pin outputs”1″.

Thus, when the address line is output, V1 and V2 two MOS tubes are used and push pull output.

When P0 outputs low 8 bit address information, it becomes a data bus. At this point, the CPU operates as the control end outputs 0, and the analog switch hits the Q non-end of the latch and enters “1” into the latch. So the Q output is 0 and V2 is off. At the same time, the control line is 0, and the gate output is 0, and the V1 is cut off.Because both V1 and V2 are cut off, pins are completely high-impedance to the outside, and as input ports, external data enters the internal bus through U6, as shown in Figure 22. (The equivalent of turning off both push-pull MOS transistors) is the real input because of the high external resistancePin. This explains why P0 is a real two wire port.

P0For ordinary IO:

When P0 is used as an ordinary IO and output, the control signal is 0, so that V1 is always in the cut-off state. The analog switch connects to Q non-output, and when used as output, the input of the latch inputs either 0 or 1 directly, and Q does not input the anti-phase signal to the input of V2. That is, when output “0”, V2 input.The terminal is “1”, V2 turn on, pin output “0”; when the output “1”, V2 input is “0”, V2 cut off, pin output high resistance 0. That is, when P0 works in the normal IO mode, the output is open drain output and there is no pull-up resistor inside.

When P0 is used as an ordinary IO and input, the control signal is 0, so that V1 is always in the cut-off state. The analog switch is connected to Q non-output, and the CPU automatically writes 1 to the latch input, then the V2 input is 0, and the V2 is cut off. It is also used as an address / data line as input.The two MOS tubes are all disconnected, pin is directly connected to U6, and the external resistance is high. It is also true input pin.

In summary, P0 is a real dual port IO, no matter which mode it works.

51P1 to P3 port of single chip microcomputer

51The internal structure of the other three ports of the microcontroller, shown in Figure 23, is much simpler than P0, without the top MOS transistor, and no address / data signal options. As the output is a leak-opening output with pull-up resistance, as the input there is pull-up resistance, so the input portExternal is not a high resistance. This explains why P1 to P3 can only be quasi two-way ports.